VLSI DESIGN
UNIT I CMOS TECHNOLOGY
Ideal I-V characteristics
C-V characteristics
Non ideal IV effects
DC transfer characteristics
CMOS Layout design
UNIT II CIRCUIT CHARACTERIZATION AND SIMULATION
Delay estimation
Logical effort and Transistor sizing
Power dissipation
Scaling
Circuit characterization
UNIT III COMBINATIONAL AND SEQUENTIAL CIRCUIT DESIGN
Low power logic design
Comparison of circuit families
Sequencing static circuits
Circuit design of latches and flip flops
Sequencing dynamic circuits
UNIT IV CMOS TESTING
Testers
Text fixtures and test programs
Silicon debug principles
Design for testability
Boundary scan
UNIT V SPECIFICATION USING VERILOG HDL
Gate primitives
Procedural assignments conditional statements
Structural gate level and Switch level modeling
Behavioral and RTL modeling
Test benches
Structural gate level description of decoder, equality detector,
comparator, priority encoder, half adder, full adder, Ripple carry adder, D
latch and D flip flop.
No comments :
Post a Comment